Faculty of Information Technology
Refer to the specific census and withdrawal dates for the semester(s) in which this unit is offered.
This unit covers the internal mechanism of computers and how they are organised and programmed. Topics include combinatorial and sequential logic, Boolean Algebra, Karnaugh maps, counters, ripple adders, tree adders, memory/addressing, busses, speed, DMA, data representation, machine arithmetic, microprogramming, caches and cache architectures, virtual memory and translation look-aside buffers, vectored interrupts, polled interrupts, pipelined architecture, superscalar architecture, data dependency, hazards, CISC, RISC, VLIW machine architectures.
At the completion of this unit, students should be able to:
Examination (3 hours): 60%; In-semester assessment: 40%
Minimum total expected workload equals 12 hours per week comprising:
(a.) Contact hours for on-campus students:
(b.) Additional requirements (all students):
See also Unit timetable information
Dr Carlo Kopp