Faculty of Engineering
|Faculty||Faculty of Engineering|
|Organisational Unit||Department of Electrical and Computer Systems Engineering|
|Offered||Clayton First semester 2014 (Day)|
|Coordinator(s)||L Kleeman (Clayton); M Ooi (Malaysia)|
The unit aims to develop a fundamental understanding of the performance, specification and fabrication of large scale digital circuits. Students will become experienced at the design, simulation, verification and debugging of complex large scale digital circuits using a Hardware Description Language (HDL) and current CAD tools with FPGA development boards. Two group design projects will be undertaken: one involving an HDL using FPGA devices and another involving custom VLSI CMOS design and simulation
Laboratory and assignment work: 40%
Examination (3 hours): 60%.
Students are required to achieve at least 45% in the total continuous assessment component (assignments, tests, mid-semester exams, laboratory reports) and at least 45% in the final examination component and an overall mark of 50% to achieve a pass grade in the unit. Students failing to achieve this requirement will be given a maximum of 45% in the unit.
2 hours lectures, 3 hours laboratory/practice classes and 7 hours private study per week
ECE2061 or TRC2500
ECE3073 or TRC3300
ECE4604, ECE5063, ECE5604