units

ECE4063

Faculty of Engineering

Undergraduate - Unit

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6 points, SCA Band 2, 0.125 EFTSL

Refer to the specific census and withdrawal dates for the semester(s) in which this unit is offered, or view unit timetables.

LevelUndergraduate
FacultyFaculty of Engineering
Organisational UnitDepartment of Electrical and Computer Systems Engineering
OfferedClayton First semester 2014 (Day)
Coordinator(s)L Kleeman (Clayton); M Ooi (Malaysia)

Synopsis

The unit aims to develop a fundamental understanding of the performance, specification and fabrication of large scale digital circuits. Students will become experienced at the design, simulation, verification and debugging of complex large scale digital circuits using a Hardware Description Language (HDL) and current CAD tools with FPGA development boards. Two group design projects will be undertaken: one involving an HDL using FPGA devices and another involving custom VLSI CMOS design and simulation

Outcomes

  • understand the evolution of complex digital integrated circuits and scaling issues
  • appreciate the fabrication processes used for producing CMOS VLSI circuits
  • understand of the uses and limitations of VLSI and HDL in the synthesis and simulation
  • develop an appreciation of different VLSI design styles and hierarchical design
  • gain a physical insight into digital circuit behaviour and performance
  • appreciate the characteristics of synchronous and self-timed design methodologies
  • understand the fundamental synchronization issues of independent digital systems
  • develop skills in VLSI and HDL large scale digital design and simulation with CAD tools
  • acquire the skill of debugging and fault finding large scale digital designs
  • appreciate how fundamentals of digital design can be applied to this rapidly changing field

Assessment

Laboratory and assignment work: 40%
Examination (3 hours): 60%.
Students are required to achieve at least 45% in the total continuous assessment component (assignments, tests, mid-semester exams, laboratory reports) and at least 45% in the final examination component and an overall mark of 50% to achieve a pass grade in the unit. Students failing to achieve this requirement will be given a maximum of 45% in the unit.

Chief examiner(s)

Workload requirements

2 hours lectures, 3 hours laboratory/practice classes and 7 hours private study per week

Prerequisites

ECE2061 or TRC2500

Co-requisites

ECE3073 or TRC3300

Prohibitions

ECE4604, ECE5063, ECE5604